Semiconductor substrate with semi-insulating polysilicon gettering site layer and process of fabrication thereof

ABSTRACT

A semi-insulating polycrystalline silicon layer containing oxygen of at least 10 percent by atom is grown on a back surface of a single crystalline silicon wafer, and achieves high gettering efficiency at a thickness less than the thickness of usual polycrystalline silicon so that the silicon substrate is less warped.

FIELD OF THE INVENTION

[0001] This invention relates to a semiconductor wafer and a process offabrication thereof and, more particularly, to a semiconductor waferwith a gettering site layer of semi-insulating polycrystalline siliconand a process of fabrication thereof.

DESCRIPTION OF THE RELATED ART

[0002] A semiconductor device has been enhanced in integration density.An integrated circuit is concurrently fabricated on a large diametersilicon wafer, and the device fabrication technologies becomescomplicated. An appropriate gettering technique is required forsemiconductor devices in the next generation.

[0003] The denuded zone intrinsic gettering is a typical getteringtechnologies for a silicon wafer. However, the denuded zone intrinsicgettering process requires long heat treatment for a large diametersilicon wafer, and the long heat treatment is costly.

[0004] A poly-back seal gettering is a kind of extrinsic getteringtechnology, and a polycrystalline silicon layer is formed on the backsurface of a silicon wafer. The gettering efficiency of thepolycrystalline silicon layer is dependent on the depositing conditionsof polycrystalline silicon. The optimization of gettering efficiency istaught by D. M. Lee et. al. in “IRON GETTERING EFFICIENCY BY APOLYSILICON LAYER IN P-TYPE CZ SILICON”, Journal of ElectrochemicalSociety, pages 820 to 830, 1994.

[0005]FIG. 1 illustrates a semiconductor structure used in theexperiments carried out by D. M. Lee et. al. The semiconductor structureconsists of a single crystalline silicon layer 1 and a polycrystallinesilicon layer 2 grown on the back surface of the single crystallinesilicon layer 1. The single crystalline silicon layer 1 is grown througha Czochalski crystal growing technology, and the polycrystalline siliconlayer 2 is grown under different conditions.

[0006] The polycrystalline silicon layer 2 of the first sample is grownto 0.8 micron thick at 700 degrees in centigrade, the polycrystallinesilicon layer 2 of the second sample is grown to 1.2 microns thick at700 degrees in centigrade, the polycrystalline silicon layer 2 of thethird sample is grown to 1.6 microns thick at 700 degrees in centigrade,and the polycrystalline silicon layer 2 of the fourth sample is grown to1.2 microns thick at 620 degrees in centigrade. Comparative samples areprepared through different gettering treatments. The first comparativesample is treated with etching instead of the deposition ofpolycrystalline silicon, and the second comparative sample is treatedwith sand blasting instead of the deposition of polycrystalline silicon.The six samples, i.e., the first sample to the fourth sample, the firstcomparative sample and the second comparative sample are contaminatedwith iron, and, thereafter, the residual iron is measured.

[0007]FIG. 2 illustrates the residual iron concentration, and FIG. 3shows a series of microphotographs Sections A, B, C and D show thecrystal structure of the second comparative sample, the crystalstructure of first sample, the crystal structure of the second sampleand the crystal structure of the third sample, respectively. As will beunderstood from FIG. 2, the thicker the polycrystalline silicon layer 2is, the larger the gettering efficiency is. 1.2 microns is the minimumthickness of the polycrystalline silicon layer 2 effective against theiron. Moreover, the low deposition temperature makes the crystal grainof the polycrystalline silicon small, and the small crystal grainreduces the gettering efficiency. The deposition around 700 degrees incentigrade is appropriate. The microphotographs teach that high-densetwin crystal takes place during the solid state growth in the thinpolycrystalline silicon layer such as the first sample. On the otherhand, a large amount of grain boundary is left in the thickpolycrystalline silicon layer such as the third sample after the CMOSheat treatment, and still has good gettering capability. Thus, thegettering efficiency is optimized by controlling the depositiontemperature and the deposition time.

[0008] As taught by the D. M. Lee, the large gettering efficiencyrequires the polycrystalline silicon of at least 1.2 microns thick, andthe thick polycrystalline silicon layer 2 tends to warp the singlecrystalline silicon wafer 1. This is the first problem inherent in theprior art poly-back seal technology.

[0009] Another problem is that the gettering efficiency is reduced in aheat treatment repeated during a fabrication process of a semiconductordevice. As described hereinbefore, much grain boundary achieves largegettering efficiency. However, the heat treatment promotes the solidphase growth in the polycrystalline layer 2, and the polycrystallinesilicon layer loses the gettering capability.

[0010] In order to restrict the solid phase growth from poly-crystal tosingle crystal, Japanese Patent Publication of Unexamined ApplicationNo. 1-235242 proposes an ion implantation of impurity serving as aninhibitor against the solid phase growth into a back surface portion ofa single crystalline silicon wafer. The ion-implantation is carried outbefore the deposition of polycrystalline silicon on the back surface ofthe single crystalline silicon wafer, and nitrogen, oxygen and argon areexamples of the inhibitor. The inhibitor prevents the polycrystallinesilicon layer from decrease of thickness during a fabrication processfor an integrated circuit. Thus, the inhibitor is effective against theheat treatment in the fabrication process of an integrated circuit.However, large gettering efficiency still requires the polycrystallinesilicon layer equal to or greater than 1.2 microns thick, and the thickpolycrystalline silicon layer is causative of the warp undesirablyproduced in the single crystalline silicon wafer.

SUMMARY OF THE INVENTION

[0011] It is therefore an important object of the present invention toprovide a semiconductor substrate, which achieve good getteringefficiency without serious warp.

[0012] It is also an important object of the present invention toprovide a process of fabricating the semiconductor substrate.

[0013] To accomplish the object, the present invention proposes to forma gettering site layer of semi-insulating polycrystalline siliconcontaining oxygen at least 10 percent by weight. The semi-insulatingpolycrystalline silicon contains oxygen at least ten percent by atom.

[0014] In accordance with one aspect of the present invention, there isprovided a semiconductor substrate used for fabrication of asemiconductor device comprising an active layer formed of singlecrystalline semiconductor material and having a first surface used forfabricating at least one electric component thereon and a second surfacereverse to the first surface, and a gettering site layer grown on thesecond surface of the active layer and formed of semi-insulatingpolycrystalline silicon containing oxygen of at least 10 percent byatom.

[0015] In accordance with another aspect of the present invention, thereis provided a process of producing a semiconductor substrate used for asemiconductor device comprising the steps of preparing an active layerof single crystalline semiconductor material, and forming a getteringsite layer formed of semi-insulating polycrystalline silicon containingoxygen of at least 10 percent by atom on one surface of the activelayer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The features and advantages of the semiconductor wafer and theprocess will be more clearly understood from the following descriptiontaken in conjunction with the accompanying drawings in which:

[0017]FIG. 1 is a cross sectional view showing the structure of asilicon wafer treated through the poly-back seal gettering;

[0018]FIG. 2 is a graph showing the residual iron concentration of thesamples disclosed in the paper;

[0019]FIG. 3 is a series of microphotographs showing the crystalstructure of samples disclosed in the paper;

[0020]FIG. 4 is a cross sectional view showing the structure of asemiconductor device fabricated on a silicon substrate according to thepresent invention;

[0021]FIGS. 5A to 5F are cross sectional views showing a process offabricating a semiconductor device according to the present invention;

[0022]FIG. 6 is a graph showing the initial break-down voltage measuredby the present inventor;

[0023]FIG. 7 is a graph showing variation of grain size in terms ofoxygen content of semi-insulating polycrystalline silicon after anannealing; and

[0024]FIG. 8 is a cross sectional view showing the structure of anothersilicon substrate according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] First Embodiment

[0026] Referring to FIG. 4 of the drawings, a semiconductor device isfabricated on a silicon substrate 11 embodying the present invention.The silicon substrate 11 comprises an active layer 12 and a getteringsite layer 13. The active layer 12 has a major surface and a backsurface reverse to the major surface, and the gettering site layer 13 isgrown on the back surface of the active layer 12. The active layer 12 isformed of single crystalline silicon, and the gettering site layer 13 isformed of semi-insulating polycrystalline silicon. The polycrystallinesilicon contains oxygen of at least 10 percent by atom, and the oxygenimparts the semi-insulating property to the polycrystalline silicon.

[0027] In this instance, the single crystalline silicon is doped withn-type impurity, and a p-type well 14 is formed in a surface portion ofthe active layer 12. A thick field oxide layer 15 defines active areas,and one of the active areas is assigned to an n-channel type fieldeffect transistor 16. Though not shown in FIG. 4, a p-channel type fieldeffect transistor is formed in another active area, and forms acomplementary field effect transistor together with the n-channel typefield effect transistor 16.

[0028] The n-channel type field effect transistor 16 includes n-typesource and drain regions 16 a and 16 b. The n-type source and drainregions 16 a and 16 b are formed in the p-type well 14, and are spacedfrom each other. The surface portion between the n-type source and drainregions 16 a and 16 b serves as a channel region. The n-channel typefield effect transistor 16 further includes a thin gate insulating layer16 c and a gate electrode 16 d. The channel region is overlain by thethin gate insulating layer 16 c, and the gate electrode 16 d is formedon the thin gate insulating layer 16 c.

[0029] A pair of side wall spacers 17 is formed on both side surfaces ofthe gate electrode 16 d, and titanium silicide layers 18 a, 18 b and 18c are formed oil the n-type source and drain regions 16 a/ 16 b and thegate electrode 16 d. The field effect transistors and the titaniumsilicide layers 18 a/ 18 b/ 18 c are covered with an inter-levelinsulating layer 19, and through-holes 19 a/ 19 b/ 19 c are formed inthe inter-level insulating layer 19. The through-holes 19 a/ 19 b/ 19 care open at the upper surface of the inter-level insulating layer 19 andat the n-type source and drain regions 16 a/ 16 b and the gate electrode16 d. Metal wires 20 a/ 20 b/ 20 c are patterned on the inter-levelinsulating layer 19, and are held in contact with the n-type source anddrain regions 16 a/ 16 b and the gate electrode 16 d through thethrough-holes 19 a/ 19 b/ 19 c, respectively. The metal wire 20 bsupplies the ground potential level to the n-type source region 16 a,and the metal wire 20 b is connected to the drain region of thep-channel type field effect transistor, and the metal wire 20 c suppliesan input signal to the gate electrode 16 d and the gate electrode of thep-channel type field effect transistor. Thus, the n-channel type fieldeffect transistor 16 and the p-channel type field effect transistor formin combination the complementary field effect transistor.

[0030] The semiconductor device shown in FIG. 4 is fabricated asfollows. First, a single crystalline silicon wafer 30 is prepared. Apart 30 a of the single crystalline silicon wafer 30 serves as theactive layer 12 assigned to the semiconductor device.

[0031] Subsequently, semi-insulating polycrystalline silicon isdeposited to 800 nanometers thick over the entire back surface of thesingle crystalline silicon wafer 30 by using a low-pressure chemicalvapor deposition technique, and forms a semi-insulating polycrystallinesilicon layer 31. A part 31 a of the semi-insulating polycrystallinesilicon layer 31 is located on the active layer 12, and serves as thegettering site layer 13. Thus, the lamination of the part 30 a of thewafer 30 and the part 31 a of the semi-insulating polycrystallinesilicon layer 31 serve as the semiconductor substrate 11.

[0032] The present inventor grew the polycrystalline silicon under thedifferent depositing conditions. The polycrystalline silicon waddeposited at 650 degrees in centigrade, and the gaseous mixture ofN₂O/SiH₄ was introduced into the reactor of the low-pressure chemicalvapor deposition system. The present inventor changed the ratio ofN₂O/SiH₄ as shown in Table 1, and measured the oxygen content. TABLE 1Oxygen content Sample Ratio of N₂O/SiH₄ at % 1 0.01 10 2 0.05 35 3 0.1035

[0033] Thus, the gas flow ratio of N₂O to SiH₄ affected the oxygencontent of the polycrystalline silicon, and the minimum gas flow ratiofor the semi-insulating polycrystalline silicon was 0.01.

[0034] Using the semiconductor substrate 11, the complementary fieldeffect transistor is fabricated. Although the p-channel type fieldeffect transistor and the n-channel type field effect transistor 16 arefabricated on the semiconductor substrate 11, description is focused onthe n-channel type field effect transistor 16.

[0035] First, the thick field oxide layer 15 is selectively grown byusing the local oxidation of silicon technology, and boron is ionimplanted into the surface portion of the active layer 12 at 300 KeV.The resultant structure is annealed at 1000 degrees in centigrade, andthe ion-implanted boron forms the p-type well 14 as shown in FIG. 5C.

[0036] The thin gate insulating layer 16 c is thermally grown to 6nanometers on the p-type well 14. Polycrystalline silicon is depositedover the entire surface of the resultant semiconductor structure, andthe polycrystalline silicon layer is patterned into the gate electrode16 d by using lithographic techniques and an etching. Insulatingmaterial such as silicon oxide is deposited over the entire surface ofthe resultant semiconductor structure, and an insulating layertopographically covers the thick field oxide layer 15, the p-type well14 and the gate electrode 16 d. The insulating layer is anisotropicallyetched away, and the side wall spacers 17 are left on both side surfacesof the gate electrode 16 d. Arsenic is ion implanted into the p-typewell 14 at dosage of 1×10⁻⁵ cm⁻² under the acceleration energy of 10KeV, and is activated through heat treatment at 950 degrees incentigrade. Then, the n-type source and drain regions 16 a and 16 b areformed in the p-type well 14 as shown in FIG. 5D.

[0037] Subsequently, titanium is deposited over the entire surface ofthe resultant semiconductor structure by using a sputtering, and atitanium layer 32 topographically extends. The first sintering iscarried out at 690 degrees in centigrade, and, thereafter, the secondsintering is carried out at 800 degrees in centigrade. The titaniumreacts with silicon during the sintering, and the titanium layer 32 ispartially converted to titanium silicide portions 32 a, 32 b and 32 c asshown in FIG. 5E.

[0038] The residual titanium is etched away, and the titanium silicidelayers 18 a/ 18 b/ 18 c are left on the n-type source region 16 a, thegate electrode 16 d and the n-type drain region 16 b, respectively.Insulating material is deposited over the entire surface of theresultant semiconductor structure, and forms the inter-level insulatinglayer 19. The inter-level insulating layer 19 is reflowed at 800 degreesin centigrade. A photo-resist etching mask (not shown) is formed on theinter-level insulating layer 19, and has openings over the n-type sourceand drain regions 16 a/ 16 b and the gate electrode 16 d. Theinter-level insulating layer 19 and the titanium silicide layers 18 a/18 c/ 18 b are selectively etched away so as to form the contact holes19 a/ 19 b/ 19 c as shown in FIG. 5F.

[0039] Conductive metal is deposited over the entire surface of theresultant semiconductor structure. The conductive metal fills thecontact holes 19 a/ 19 b/ 19 c, and swells into a conductive metallayer. A photo-resist etching mask (not shown) is provided on theconductive metal layer, and the conductive metal layer is patterned intothe metal wires 20 a, 20 b and 20 c as shown in FIG. 4.

[0040] The present inventor fabricated samples I, II and III of thesemiconductor device through the process described hereinbefore, and twocomparative samples were further prepared through the same process. Thesingle crystal silicon wafers were obtained from a single crystalsilicon rod grown through a floating zone method. The first comparativesample was without any gettering site layer of polycrystalline silicon,and the second comparative sample had a gettering site layer ofpolycrystalline silicon taught by D. M. Lee et al. The thickness and theoxygen content were summarized in Table 2. TABLE 2 Oxygen (at %) SampleI  10 Sample II  35 Sample III 55

[0041] After the fabrication of the semiconductor device, the firstcomparative sample, the second comparative sample and samples I, II andIII were contaminated with iron. The present inventor applied potentialto the gate electrodes 16 d of each sample, and measured the initialbreak-down voltage of the gate insulating layer 16 c. The initialbreak-down voltage was plotted in FIG. 6, and the gettering site layersof the semi-insulating polycrystalline silicon were superior to theprior art gettering site layer of polycrystalline silicon. The initialbreakdown voltage was increased together with the oxygen content of thesemi-insulating polycrystalline silicon.

[0042] The present inventor investigated the influence of oxygen on thegrain size after an annealing. The present inventor treated the samplesI. II and III with heat, and measured the grain size. Plots PL1, PL2 andPL3 were indicative of the variation in grain size of polycrystallinesilicon for the samples I, II and III, respectively. It was understoodfrom plots PL1, PL2 and PL3 that the grain size was stable until 1000degrees in centigrade, and the stability was dependent on the oxygencontent. The oxygen formed a silicon oxide layer along the grainboundary, and the silicon oxide layer prevented the polycrystallinesilicon grains from solid phase growth. The large gettering efficiencywas derived from the stability of grain size. The grain size wasdrastically grown in the prior art gettering site layer ofpolycrystalline silicon proposed by D. M. Lee (see FIG. 3). This meantthat the polycrystalline silicon did not contain the oxygen of at least10 percent by weight.

[0043] The present inventor further investigated the gettering sitelayer of semi-insulating polycrystalline silicon and the prior artgettering site layer proposed by D. M. Less et al in view of warp. Whenthe gettering site layer of semi-insulating polycrystalline silicon wasequal in gettering efficiency to the prior art gettering site layer ofpolycrystalline silicon, the thickness of the semi-insulatingpolycrystalline silicon was less than that of the prior artpolycrystalline silicon, and the warp was decreased.

[0044] As will be understood from the foregoing description, thegettering site layer of semi-insulating polycrystalline silicondecreases the warp of the semiconductor substrate without reduction ofgettering efficiency.

[0045] Second Embodiment

[0046]FIG. 8 illustrates the structure of another semiconductorsubstrate 40 embodying the present invention. The semiconductorsubstrate 40 is produced as follows. First, a single crystalline siliconwafer 41 is prepared, and semi-insulating boron-doped polycrystallinesilicon is grown to 800 nanometers thick at 650 degrees in centigrade byusing a low-pressure chemical vapor deposition. Material gas containsN₂O, SiH₄ and B₂H₆. The ratio of N₂O/SiH₄ is adjusted to 0.05. As aresult, a semi-insualting boron-doped polycrystalline silicon layer isformed on the back surface of the single crystalline silicon wafer 41,and serves as a gettering site layer 42. Using the semiconductorsubstrate 40, a complementary field effect transistor is fabricated asfollows. Description is focused on an n-channel enhancement type fieldeffect transistor as similar to the first embodiment. A thick fieldoxide layer is grown by using the local oxidation of silicon techniques,and born is ion implanted into a surface portion of the semiconductorsubstrate 40 under the acceleration energy of 300 KeV. The resultantsemiconductor structure is treated with heat at 1000 degrees incentigrade, and the boron forms a p-type well.

[0047] A thin gate insulating layer is grown to 6 nanometers thick, anda gate electrode and side wall spacers are formed. Arsenic is ionimplanted into the p-type well in a self-aligned manner with the sidewall spacers at dosage of 1×10¹⁵ cm⁻² under the acceleration energy of10 KeV, and the arsenic is activated through an annealing at 950 degreesin centigrade. The arsenic forms a source region and a drain region.

[0048] Titanium is deposited over the entire surface of the resultantsemiconductor structure, and titanium silicide layers are produced onthe source/drain regions and the gate electrode through the firstsintering at 690 degrees in centigrade and the second sintering at 800degrees in centigrade. The residual titanium is etched away.

[0049] An inter-level insulating layer is formed over the resultantsemiconductor structure, and is reflowed at 800 degrees in centigrade.Contact holes are formed in the inter-level insulating layer, and reachthe source and drain regions and the gate electrode through the titaniumsilicide layers. Conductive metal is deposited over the entire surfaceof the resultant semiconductor structure, and the conductive metal layeris patterned into metal wires.

[0050] In the second embodiment, the boron is doped into thesemi-insulating polycrystalline silicon layer. The boron is replaceablewith phosphorous. The phosphorous also enhances the gettering capabilityof the semi-insulating polycrystalline silicon layer.

[0051] The semi-insulating polycrystalline silicon layer 42 is dopedwith boron, and the boron enhances the gettering efficiency of thesemi-insulating polycrystalline silicon. As a result, the manufacturercan decrease the gettering site layer, and the thin gettering site layerreduces the warp.

[0052] Although particular embodiments of the present invention havebeen shown and described, it will be obvious to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the present invention.

[0053] For example, the boron or the phosphorous may be introduced intothe semi-insulating polycrystalline silicon layer after the growth.

What is claimed is:
 1. A semiconductor substrate used for fabrication of a semiconductor device, comprising: an active layer formed of single crystalline semiconductor material and having a first surface used for fabricating at least one electric component thereon and a second surface reverse to said first surface; and a gettering site layer grown on said second surface of said active layer, and formed of semi-insulating polycrystalline silicon containing oxygen of at least 10 percent by atom.
 2. The semiconductor substrate as set forth in claim 1 , in which said active layer is formed of single crystalline silicon.
 3. The semiconductor substrate as set forth in claim 1 , in which said active layer is formed of single crystalline silicon, and boron is doped into the semi-insulating polycrystalline silicon.
 4. The semiconductor substrate as set forth in claim 1 , in which said active layer is formed of single crystalline silicon, and phosphorous is doped into the semi-insulating polycrystalline silicon.
 5. The semiconductor substrate as set forth in claim 1 , in which said gettering site layer is less than 1.2 microns thick.
 6. A process of producing a semiconductor substrate used for a semiconductor device, comprising the steps of: a) preparing an active layer of single crystalline semiconductor material; and b) forming a gettering site layer formed of semi-insulating polycrystalline silicon containing oxygen of at least 10 percent by atom on one surface of said active layer.
 7. The process as set forth in claim 6 , in which said single crystalline semiconductor material is single crystalline silicon.
 8. The process as set forth in claim 6 , in which said single crystalline semiconductor layer is formed of single crystalline silicon, and boron is doped into the semi-insulating polycrystalline silicon.
 9. The process as set forth in claim 8 , in which said boron is introduced in said semi-insulating polycrystalline silicon during a growth in said step b).
 10. The process as set forth in claim 6 , in which said single crystalline semiconductor layer is formed of single crystalline silicon, and phosphorous is doped into the semi-insulating polycrystalline silicon.
 11. The process as set forth in claim 10 , in which said phosphorous is introduced in said semi-insulating polycrystalline silicon during a growth in said step b).
 12. The process as set forth in claim 6 , in which said semi-insulating polycrystalline silicon layer is grown to a certain thickness less than 1.2 microns. 